Gateware PHY

Pure-gateware, UTMI-compatible Full Speed PHY.

class sol_usb.gateware.interface.gateware_phy.phy.GatewarePHY(*args: Any, src_loc_at: int = 0, **kwargs: Any)

Gateware that implements a UTMI-compatible transceiver using raw FPGA I/O.

Clock Domains

usb:

Our 12 MHz USB clock domain which will match each of the signals below. Should be phase-related to the 48MHz clock (e.g. divided down from it) to avoid the need for explicit synchronization on clock domain crossings.

usb_io:

The core 48MHz clock domain in which USB clock recovery and sampling is performed. Must be phase related to our usb clock domain.

ivar tx_data:

data to be transmitted; valid when tx_valid is asserted

vartype tx_data:

Signal(8), input

ivar tx_valid:

asserted when data is to be transmitted; indicates the data_in byte is valid; de-asserting this line terminates the transmission

vartype tx_valid:

Signal(), input

ivar tx_ready:

indicates the the PHY is ready to accept a new byte of data, and that the transmitter should move on to the next byte after the given cycle

vartype tx_ready:

Signal(), output

ivar rx_data:

data received from the PHY; valid when rx_valid is asserted

vartype rx_data:

Signal(8), output

ivar rx_valid:

indicates that the data present on rx_data is new and valid data; goes high for a single usb clock cycle to indicate new data is ready

vartype rx_valid:

Signal(), output

ivar rx_active:

indicates that the PHY is actively receiving data from the host; data is only valid when :attr:rx_valid is high

vartype rx_active:

Signal(), output

ivar rx_error:

indicates that an error has occurred in the current transmission

vartype rx_error:

Signal(), output

ivar rx_complete:

strobe that goes high for one cycle when a packet rx is complete

vartype rx_complete:

Signal(), output:

line_state: Signal(2), output

Indicates the current state of the D+ and D- lines. Matches the UTMI specification values, where 0 = SE0, 1 = K, and 2 = J.

vbus_valid: Signal(), output

Indicates that a valid VBUS signal is present. This signal is valid iff the I/O parameter contains a vbus_valid element; otherwise it is hard connected to ‘1’

session_end: Signal(), output

Indicates that no VBUS signal is present. This signal is valid iff the I/O parameter contains a vbus_valid element; otherwise it is hard connected to ‘0’

xcvr_select: Signal(2), input

Selects the active USB speed. This transceiver only functions as a full speed transceiver; so this signal is effectively ignored. To support connection to high-speed gateware, this module will prevent the USB lines from being driven when this signal is 0b00; allowing the gateware to attempt a high-speed detection handshake without adverse affect.

term_select: Signal(), input

When asserted, this will connect the device’s full speed pull-up resistor.

op_mode: Signal(2), input

Selects the operating mode of the UTMI transceiver. A value of 0 causes normal operations; a value of 1 prevents D+ and D- from being driven; and a value of 2 disables bit-stuffing.

dm_pulldown: Signal(), input

When asserted, this will indicate that the host-mode’s D- pulldown should be connected.

dm_pulldown: Signal(), input

When asserted, this will indicate that the host-mode’s D+ pulldown should be connected.

param io:

A record containing the raw I/O signals to be used to drive our I/O-based USB connection. The d_p and d_n signals are mandatory; the pullup, pulldown, and vbus_valid signals are optional.

type io:

Record(d_p, d_n, [pullup], [pulldown], [vbus_valid])