PIPE

USB3 PIPE interfacing gateware.

class sol_usb.gateware.interface.pipe.PIPEInterface(*args, src_loc_at: int = 0, **kwargs)

Interface present on hardware that implements the PHY Interface for PCI Express and USB 3.0 (PIPE).

This interface is compliant with the PHY Interface For the PCI Express and USB 3.0 Architectures, Version 3.0 specification. Unless otherwise noted, the descriptions of the signals as stated in this specification take precedence over the ones provided here.

The directions of the signals are given from the PHY perspective, i.e. a signal described as an ‘output’ is driven by the PHY and received by the MAC.

Parameters:

  • width (int) – Interface width, in symbols.

  • Ports

  • -----

  • reset (Signal(), input) – Active-high, asynchronous reset for the PHY receiver and transmitter.

  • clk (Signal(), input) – Reference clock for the PHY receiver and transmitter. The specifications for this clock (frequency, jitter, phase relationship to other clocks) are PHY implementation dependent and must be specified by the implementation.

  • pclk (Signal(), output) – Clock for the PHY interface. Unless otherwise specified, all other signals are synchronous to the rising edge of this clock. This clock is derived from the reference clock; if the reference clock is spread spectrum modulated, so will be the interface clock. The frequency of this clock depends on the phy_mode and rate inputs. Note that the supported combinations of phy_mode and rate are PHY implementation dependent.

  • tx_data (Signal(width * 8), input)

  • tx_datak (Signal(width), input) – Transmit data bus. Bits [7:0] are the first symbol to be transmitted, bits [15:8] (if any) are the second symbol, and so on.

  • rx_data (Signal(width * 8), output)

  • rx_datak (Signal(width), output) – Receive data bus. Bits [7:0] are the first symbol that has been received, bits [15:8] (if any) are the second symbol, and so on.

  • phy_mode (Signal(2), input) – PHY operating mode; 0 for PCI Express, 1 for SuperSpeed USB. The allowed values for this input are PHY implementation dependent. The PHY must be reset after changing this input.

  • elas_buf_mode (Signal(1), input) – Elastic buffer operating mode; 0 for Nominal Half-full, 1 for Nominal Empty. The allowed values for this input are PHY implementation dependent. The PHY must be reset after changing this input.

  • rate (Signal(1), input) – Link signaling rate; 0 for 2.5 GT/s, 1 for 5 GT/s. The allowed values for this input are PHY implementation dependent. Whether changing this signal affects the pclk frequency or the effective data bus width is PHY implementation dependent. The change of this input is acknowledged by a single-cycle assertion of phy_status.

  • power_down (Signal(2), input) – Protocol-specific power management mode, as per the PIPE specification. This signal is synchronous to pclk if the clock is running, and asynchronous otherwise. The change of this input is acknowledged by a single-cycle assertion of phy_status if pclk is running, or by deassertion of phy_status otherwise.

  • tx_deemph (Signal(2), input) – Transmitter de-emphasis level; 0 for -6 dB, 1 for -3.5 dB, 2 for 0 dB. The allowed values for this input are PHY implementation dependent.

  • tx_margin (Signal(3), input) – Transmitter voltage levels, as per the PIPE specification. The allowed values for this input and their meanings are PHY implementation dependent.

  • tx_swing (Signal(1)) – Transmitter voltage swing level. The allowed values for this input and their meanings are PHY implementation dependent.

  • tx_detrx_lpbk (Signal(), input)

  • tx_elec_idle (Signal(), input) – Protocol-specific transmit control signals, as per the PIPE specification. Depending on the state of phy_mode and power_down inputs, these inputs direct the PHY transmitter to transmit data from the transmit data bus, loop back received data, go into Electrical Idle, transmit beacon or LFPS signaling, or perform a receiver detection operation. These signals are synchronous to pclk if the clock is running, and asynchronous otherwise. The completion of a receiver detection operation is acknowledged by a single-cycle assertion of phy_status if pclk is running, or by asserting phy_status until the MAC deasserts tx_detrx_lpbk otherwise.

  • tx_compliance (Signal(), input) – If asserted, sets the running disparity to negative for the first symbol on the transmit data bus. This signal is implemented only for PHYs that can operate in the PCI Express mode.

  • tx_ones_zeroes (Signal(), input) – If asserted, the PHY transmits an alternating sequence of 50-250 ones and 50-250 zeroes instead of the data on the transmit data bus. This signal is implemented only for PHYs that can operate in the SuperSpeed USB mode.

  • rx_polarity (Signal(), input) – If asserted, the PHY receiver inverts the received serial data.

  • rx_eq_training (Signal(), input) – If asserted, the PHY receiver bypasses normal operation to perform equalization training. Whether this signal is implemented is PHY implementation dependent.

  • rx_termination (Signal(), input) – If asserted, the PHY receiver presents receiver terminations. Whether this signal is implemented is PHY implementation dependent.

  • phy_status (Signal(), output) – PHY operation completion status, as per the PIPE specification. This signal is synchronous to pclk if the clock is running, and asynchronous otherwise.

  • rx_valid (Signal(), output) – If asserted, the PHY receiver has symbol lock and there is valid data on the data bus.

  • rx_status (Signal(3), output) – Indicates one of the four possible receiver errors (8b10b decode error, disparity error, elastic buffer overflow or underflow), the addition or removal of symbols as a part of elastic buffer management, or the completion of a receiver detection operation. This signal is synchronous to pclk if the clock is running, and asynchronous otherwise.

  • rx_elec_idle (Signal(), output) – If asserted, depending on the state of phy_mode and power_down inputs, indicates detection of Electrical Idle, beacon signaling, or LFPS signaling. This signal is asynchronous.

  • power_present (Signal(), output) – If asserted, voltage is present on Vbus. Whether this signal is implemented is PHY implementation dependent.

class sol_usb.gateware.interface.pipe.AsyncPIPEInterface(*args, src_loc_at: int = 0, **kwargs)

Gateware that transfers PIPE interface signals between clock domains.

The PIPE specification defines the PHY interface signals to be synchronous to a PHY-generated clock pclk, and asynchronous if pclk is not running. The MAC will typically not be clocked by pclk for the following non-exhaustive list of reasons:

  • The MAC implements P2 (for PCI Express) or P3 (for SuperSpeed USB) power states where the PHY-generated clock is not running;

  • The PHY-generated clock is faster than the maximum frequency at which the MAC can run;

  • The MAC implements rate switching (for PCI Express), and needs to support PHYs that change the PHY-generated clock frequency depending on the rate;

  • The PHY is required to use a spread spectrum clock in the SuperSpeed USB mode, and this would interfere with the MAC operation;

  • etc.

This gateware transfers the PIPE interface signals between the PHY and MAC clock domains, optionally performing gearing to adapt the PHY data bus width and interface clock rate to the MAC capabilities. With the exception of reset, clk and pclk, all of the signals in this gateware are synchronous to the specified Torii clock domain, ss by default. The pclk signal is driven by the clock of this domain.

This gateware does not currently support asynchronous signaling in the deepest PHY power state.

class sol_usb.gateware.interface.pipe.GearedPIPEInterface(*args, src_loc_at: int = 0, **kwargs)

Module that presents a post-gearing PIPE interface, performing gearing in I/O hardware.

This module presents a public interface that’s identical to a standard PIPE PHY, with the following exceptions:

  • tx_data is 32 bits wide, rather than 16

  • tx_datak is 4 bits wide, rather than 2

  • rx_data is 32 bits wide, rather than 16

  • rx_datak is 4 bits wide, rather than 2

  • phy_status is 2 bits wide, rather than 1

  • rx_status is now an array of two 3-bit signals

This module requires that a half-rate / 125MHz clock that’s in phase with the pipe_io clock be provided to the pipe domain. This currently must be handled per-device, so it is the responsibility of the platform’s clock domain generator.

This module optionally can connect the PIPE I/O clock (pclk) to the design’s clocking network. This configuration is recommended.

Parameters:

  • pipe (PIPE I/O resource) – The raw PIPE interface to be worked with.

  • handle_clocking (boolean, optional) – If true or not provided, this module will attempt to handle some clock connections for you. This means that ClockSignal(‘pipe_io’) will be automatically driven by the PHY’s clock (pclk), and tx_clk will automatically be tied to ClockSignal(‘pipe’).