SerDes PHY - XC7¶

Important

This module has been deprecated and moved to torii-usb, please see the migration guide.

Soft PIPE backend for the Xilinx 7 Series GTP transceivers.

class sol_usb.gateware.interface.serdes_phy.xc7_gtp.XC7GTPSerDesPIPE(*args: Any, src_loc_at: int = 0, **kwargs: Any)¶

Wrapper around the core GTP SerDes that adapts it to the PIPE interface.

The implementation-dependent behavior of the standard PIPE signals is described below:

width :: Interface width. Always 2 symbols.
clk :: Reference clock for the PHY receiver and transmitter. Could be routed through fabric, or connected to the output of an IBUFDS_GTE2 block.
pclk :: Clock for the PHY interface. Frequency is always 250 MHz.
phy_mode :: PHY operating mode. Only SuperSpeed USB mode is supported.
elas_buf_mode :: Elastic buffer mode. Only nominal half-full mode is supported.
rate :: Link signaling rate. Only 5 GT/s is supported.
power_down :: Power management mode. Only P0 is supported.
tx_deemph :: Transmitter de-emphasis level. Only TBD is supported.
tx_margin :: Transmitter voltage levels. Only TBD is supported.
tx_swing :: Transmitter voltage swing level. Only full swing is supported.

tx_detrx_lpbk : tx_elec_idle :

Transmit control signals. Loopback and receiver detection are not implemented.

tx_compliance : tx_ones_zeroes :

These inputs are not implemented.

power_present :: This output is not implemented. External logic may drive it if necessary.

Soft PIPE backend for the Xilinx 7 Series GTX transceivers.

class sol_usb.gateware.interface.serdes_phy.xc7_gtx.XC7GTXSerDesPIPE(*args: Any, src_loc_at: int = 0, **kwargs: Any)¶

Wrapper around the core GTX SerDes that adapts it to the PIPE interface.

The implementation-dependent behavior of the standard PIPE signals is described below:

width :: Interface width. Always 2 symbols.
clk :: Reference clock for the PHY receiver and transmitter. Could be routed through fabric, or connected to the output of an IBUFDS_GTE2 block.
pclk :: Clock for the PHY interface. Frequency is always 250 MHz.
phy_mode :: PHY operating mode. Only SuperSpeed USB mode is supported.
elas_buf_mode :: Elastic buffer mode. Only nominal half-full mode is supported.
rate :: Link signaling rate. Only 5 GT/s is supported.
power_down :: Power management mode. Only P0 is supported.
tx_deemph :: Transmitter de-emphasis level. Only TBD is supported.
tx_margin :: Transmitter voltage levels. Only TBD is supported.
tx_swing :: Transmitter voltage swing level. Only full swing is supported.

tx_detrx_lpbk : tx_elec_idle :

Transmit control signals. Loopback and receiver detection are not implemented.

tx_compliance : tx_ones_zeroes :

These inputs are not implemented.

power_present :: This output is not implemented. External logic may drive it if necessary.