SerDes PHY - ECP5

Soft PIPE backend for the Lattice ECP5 SerDes.

class sol_usb.gateware.interface.serdes_phy.ecp5.ECP5SerDesConfigInterface(*args, src_loc_at: int = 0, **kwargs)

Module that interfaces with the ECP5’s SerDes Client Interface (SCI).

class sol_usb.gateware.interface.serdes_phy.ecp5.ECP5SerDesRegisterTranslator(*args, src_loc_at: int = 0, **kwargs)

Interface that converts control signals into SerDes register reads and writes.

class sol_usb.gateware.interface.serdes_phy.ecp5.ECP5SerDesEqualizerInterface(*args, src_loc_at: int = 0, **kwargs)

Interface that controls the ECP5 SerDes’ equalization settings via SCI.

Currently takes full ownership of the SerDes Client Interface.

This unit allows runtime changing of the SerDes’ equalizer settings.

  • enable_equalizer (Signal(), input) – Assert to enable the SerDes’ equalizer.

  • equalizer_pole (Signal(4), input) – Selects the pole used for the input equalization; ostensibly shifting the knee on the linear equalizer. The meaning of these values are not documented by Lattice.

  • equalizer_level (Signal(2), input) – Selects the equalizer’s gain. 0 = 6dB, 1 = 9dB, 2 = 12dB, 3 = undocumented. Note that the value 3 is marked as ‘not used’ in the SerDes manual; but then used anyway by Lattice’s reference designs.

class sol_usb.gateware.interface.serdes_phy.ecp5.ECP5SerDesEqualizer(*args, src_loc_at: int = 0, **kwargs)

Interface that controls the ECP5 SerDes’ equalization settings via SCI.

Currently takes full ownership of the SerDes Client Interface.

Ideally, an analog-informed receiver equalization would occur during USB3 link training. However, we’re at best a simulacrum of a USB3 PHY built on an undocumented SerDes; so we’ll do the best we can by measuring 8b10b encoding errors and trying various equalization settings until we’ve ‘minimized’ bit error rate.

  • train_equalizer (Signal(), input) – When high, this unit attempts to train the Rx linear equalizer in order to minimize errors. This should be held only when a spectrally-rich data set is present, such as a training sequence.

  • encoding_error_detected (Signal(), input) – Strobe; should be high each time the SerDes encounters an 8b10b encoding error.

class sol_usb.gateware.interface.serdes_phy.ecp5.ECP5SerDesResetSequencer(*args, src_loc_at: int = 0, **kwargs)

Reset sequencer; ensures that the PLL, CDR, and PCS all start correctly.

class sol_usb.gateware.interface.serdes_phy.ecp5.ECP5SerDes(*args, src_loc_at: int = 0, **kwargs)

Abstraction layer for working with the ECP5 SerDes.

class sol_usb.gateware.interface.serdes_phy.ecp5.ECP5SerDesPIPE(*args, src_loc_at: int = 0, **kwargs)

Wrapper around the core ECP5 SerDes that adapts it to the PIPE interface.

The implementation-dependent behavior of the standard PIPE signals is described below:

width :

Interface width. Always 2 symbols.

clk :

Reference clock for the PHY receiver and transmitter. Could be routed through fabric, or connected to the output of an EXTREFB block. Frequency must be one of 250 MHz, 200 MHz, or 312.5 MHz.

pclk :

Clock for the PHY interface. Frequency is always 250 MHz.

phy_mode :

PHY operating mode. Only SuperSpeed USB mode is supported.

elas_buf_mode :

Elastic buffer mode. Only nominal half-full mode is supported.

rate :

Link signaling rate. Only 5 GT/s is supported.

power_down :

Power management mode. Only P0 is supported.

tx_deemph :

Transmitter de-emphasis level. Only TBD is supported.

tx_margin :

Transmitter voltage levels. Only TBD is supported.

tx_swing :

Transmitter voltage swing level. Only full swing is supported.

tx_detrx_lpbk : tx_elec_idle :

Transmit control signals. Loopback and receiver detection are not implemented.

tx_compliance : tx_ones_zeroes : rx_eq_training :

These inputs are not implemented.

power_present :

This output is not implemented. External logic may drive it if necessary.