SerDes PHY
SerDes-based USB3 PIPE PHY.
- class sol_usb.gateware.interface.serdes_phy.ECP5SerDesPIPE(*args, src_loc_at: int = 0, **kwargs)
Wrapper around the core ECP5 SerDes that adapts it to the PIPE interface.
The implementation-dependent behavior of the standard PIPE signals is described below:
- width :
Interface width. Always 2 symbols.
- clk :
Reference clock for the PHY receiver and transmitter. Could be routed through fabric, or connected to the output of an
EXTREFBblock. Frequency must be one of 250 MHz, 200 MHz, or 312.5 MHz.- pclk :
Clock for the PHY interface. Frequency is always 250 MHz.
- phy_mode :
PHY operating mode. Only SuperSpeed USB mode is supported.
- elas_buf_mode :
Elastic buffer mode. Only nominal half-full mode is supported.
- rate :
Link signaling rate. Only 5 GT/s is supported.
- power_down :
Power management mode. Only P0 is supported.
- tx_deemph :
Transmitter de-emphasis level. Only TBD is supported.
- tx_margin :
Transmitter voltage levels. Only TBD is supported.
- tx_swing :
Transmitter voltage swing level. Only full swing is supported.
tx_detrx_lpbk : tx_elec_idle :
Transmit control signals. Loopback and receiver detection are not implemented.
tx_compliance : tx_ones_zeroes : rx_eq_training :
These inputs are not implemented.
- power_present :
This output is not implemented. External logic may drive it if necessary.
- class sol_usb.gateware.interface.serdes_phy.XC7GTPSerDesPIPE(*args, src_loc_at: int = 0, **kwargs)
Wrapper around the core GTP SerDes that adapts it to the PIPE interface.
The implementation-dependent behavior of the standard PIPE signals is described below:
- width :
Interface width. Always 2 symbols.
- clk :
Reference clock for the PHY receiver and transmitter. Could be routed through fabric, or connected to the output of an
IBUFDS_GTE2block.- pclk :
Clock for the PHY interface. Frequency is always 250 MHz.
- phy_mode :
PHY operating mode. Only SuperSpeed USB mode is supported.
- elas_buf_mode :
Elastic buffer mode. Only nominal half-full mode is supported.
- rate :
Link signaling rate. Only 5 GT/s is supported.
- power_down :
Power management mode. Only P0 is supported.
- tx_deemph :
Transmitter de-emphasis level. Only TBD is supported.
- tx_margin :
Transmitter voltage levels. Only TBD is supported.
- tx_swing :
Transmitter voltage swing level. Only full swing is supported.
tx_detrx_lpbk : tx_elec_idle :
Transmit control signals. Loopback and receiver detection are not implemented.
tx_compliance : tx_ones_zeroes :
These inputs are not implemented.
- power_present :
This output is not implemented. External logic may drive it if necessary.
- class sol_usb.gateware.interface.serdes_phy.XC7GTXSerDesPIPE(*args, src_loc_at: int = 0, **kwargs)
Wrapper around the core GTX SerDes that adapts it to the PIPE interface.
The implementation-dependent behavior of the standard PIPE signals is described below:
- width :
Interface width. Always 2 symbols.
- clk :
Reference clock for the PHY receiver and transmitter. Could be routed through fabric, or connected to the output of an
IBUFDS_GTE2block.- pclk :
Clock for the PHY interface. Frequency is always 250 MHz.
- phy_mode :
PHY operating mode. Only SuperSpeed USB mode is supported.
- elas_buf_mode :
Elastic buffer mode. Only nominal half-full mode is supported.
- rate :
Link signaling rate. Only 5 GT/s is supported.
- power_down :
Power management mode. Only P0 is supported.
- tx_deemph :
Transmitter de-emphasis level. Only TBD is supported.
- tx_margin :
Transmitter voltage levels. Only TBD is supported.
- tx_swing :
Transmitter voltage swing level. Only full swing is supported.
tx_detrx_lpbk : tx_elec_idle :
Transmit control signals. Loopback and receiver detection are not implemented.
tx_compliance : tx_ones_zeroes :
These inputs are not implemented.
- power_present :
This output is not implemented. External logic may drive it if necessary.