Gateware PHY - Transmitter

class sol_usb.gateware.interface.gateware_phy.transmitter.TxShifter(*args, src_loc_at: int = 0, **kwargs)

Transmit Shifter

TxShifter accepts parallel data and shifts it out serially.

Parameters:

  • constructor. (Input ports are passed in via the)

  • width (int) – Width of the data to be shifted.

  • Ports (Output)

  • -----------

  • constructor.

  • i_data (Signal(width)) – Data to be transmitted.

  • i_enable (Signal(), input) – When asserted, shifting will be allowed; otherwise, the shifter will be stalled.

  • Ports

  • ------------

  • flopped. (Output ports are data members of the module. All outputs are)

  • o_data (Signal()) – Serial data output.

  • o_empty (Signal()) – Asserted the cycle before the shifter loads in more i_data.

  • o_get (Signal()) – Asserted the cycle after the shifter loads in i_data.

class sol_usb.gateware.interface.gateware_phy.transmitter.TxNRZIEncoder(*args, src_loc_at: int = 0, **kwargs)

NRZI Encode

In order to ensure there are enough bit transitions for a receiver to recover the clock usb uses NRZI encoding. This module processes the incoming dj, dk, se0, and valid signals and decodes them to data values. It also pipelines the se0 signal and passes it through unmodified.

https://www.pjrc.com/teensy/beta/usb20.pdf, USB2 Spec, 7.1.8 https://en.wikipedia.org/wiki/Non-return-to-zero

Clock Domain

usb_48 : 48MHz

Input Ports

i_validSignal()

Qualifies oe, data, and se0.

i_oeSignal()

Indicates that the transmit pipeline should be driving USB.

i_dataSignal()

Data bit to be transmitted on USB. Qualified by o_valid.

i_se0Signal()

Overrides value of o_data when asserted and indicates that SE0 state should be asserted on USB. Qualified by o_valid.

Output Ports

o_usbpSignal()

Raw value of USB+ line.

o_usbnSignal()

Raw value of USB- line.

o_oeSignal()

When asserted it indicates that the tx pipeline should be driving USB.

class sol_usb.gateware.interface.gateware_phy.transmitter.TxBitstuffer(*args, src_loc_at: int = 0, **kwargs)

Bitstuff Insertion

Long sequences of 1’s would cause the receiver to lose it’s lock on the transmitter’s clock. USB solves this with bitstuffing. A ‘0’ is stuffed after every 6 consecutive 1’s.

The TxBitstuffer is the only component in the transmit pipeline that can delay transmission of serial data. It is therefore responsible for generating the bit_strobe signal that keeps the pipe moving forward.

https://www.pjrc.com/teensy/beta/usb20.pdf, USB2 Spec, 7.1.9 https://en.wikipedia.org/wiki/Bit_stuffing

Clock Domain

usb_12 : 48MHz

Input Ports

i_dataSignal()

Data bit to be transmitted on USB.

Output Ports

o_dataSignal()

Data bit to be transmitted on USB.

o_stallSignal()

Used to apply backpressure on the tx pipeline.